Silicon Carbide (SiC) Gate Turn-Off Thyristors (GTOs) are considered to be an appropriate device for high power, high temperature, and high frequency applications. One of the major challenges in the fabrication of SiC GTOs is the phenomenon of current gain instability on the top transistor, which is partially attributed to surface recombination. More specifically, FIGS. 1A through 1C illustrate a conventional process for fabricating a GTO 10. As illustrated in FIG. 1A, fabrication of the GTO 10 begins with a structure 12 including a number of semiconductor layers 14 through 22 of a desired semiconductor material having alternating doping types. The semiconductor layers 14 through 22 are eptiaxially grown layers of the desired semiconductor material. More specifically, the structure 12 includes an N-type semiconductor layer 14 that is highly doped, a P-type semiconductor layer 16 on the N-type semiconductor layer 14, an N-type base layer 18 epitaxially grown on the P-type semiconductor layer 16, a P-type semiconductor layer 20 that is highly doped and on the N-type base layer 18, and a P-type semiconductor layer 22 that is very highly doped and on the P-type semiconductor layer 20.
As illustrated in FIG. 1B, the P-type semiconductor layers 20 and 22 are etched down to the N-type base layer 18 such that, after etching, the P-type semiconductor layers 20 and 22 form an anode of the GTO 10. The bottom surface of the N-type semiconductor layer 14 forms a cathode of the GTO 10. As illustrated, as a result of the etching process, there is substantial damage to the crystalline structure both at sidewall surfaces 24 of the P-type semiconductor layers 20 and 22 forming the anode of the GTO 10 and at a surface 26 of the N-type base layer 18. Lastly, as illustrated in FIG. 1C, N+ wells 28 are formed in the N-type base layer 18 as illustrated via ion implantation. The N+ wells 28 form gates of the GTO 10. At this point, fabrication of the GTO 10 is complete.
During operation, when a current (IG) is applied to the gates, electrons are injected into the N-type base layer 18 and travel through the N-type base layer 18 into the P-type semiconductor layers 20 and 22 forming the anode of the GTO 10. These electrons attract holes from the P-type semiconductor layers 20 and 22 forming the anode. Because the P-type semiconductor layers 20 and 22 are highly doped, a single electron injected into the N-type base layer 18 attracts multiple holes from the P-type semiconductor layers 20 and 22. As a result, holes that are attracted by the electrons injected into the N-type base layer 18 that do not combine with the electrons injected into the N-type base layer 18 flow from the anode of the GTO 10 to the cathode of the GTO 10, thereby creating a current flowing through the GTO 10.
However, the damage to the crystalline structure due to the etching process to form the anode of the GTO 10 results in interface charge, or surface traps, both at the sidewall surfaces 24 of the P-type semiconductor layers 20 and 22 and the surface 26 of the N-type base layer 18. This interface charge attracts and traps electrons injected into the N-type base layer 18 in a phenomenon referred to as surface recombination. This surface recombination decreases a gain (β) of a top transistor of the GTO 10. The top transistor of the GTO 10 is a PNP transistor formed by the semiconductor layers 16, 18, and 20. The GTO 10 also includes a bottom transistor, which is an NPN transistor formed by the semiconductor layers 14, 16, and 18. By decreasing the gain (β) of the top transistor of the GTO 10, surface recombination also increases a turn-on current (IG,TURN-ON) required at the gate of the GTO 10 in order to turn on the GTO 10. Further, during operation, the amount of interface charge, or surface traps, increases, thereby resulting in instability in a current gain of the GTO 10 and thus the turn-on current (IG,TURN-ON) of the GTO 10. In addition, surface recombination increases an on-resistance of the GTO 10. As such, there is a need for a GTO structure that eliminates or at least mitigates surface recombination.
Another issue that arises during fabrication is less than ideal yield due to non-uniform etching. More specifically, as illustrated in FIG. 2, a number of GTOs 10 are fabricated on a semiconductor wafer 30. However, when etching the P-type semiconductor layers 20 and 22 via Reactive Ion Etching (RIE) or a similar etching process to form the anodes of the GTOs 10, etching occurs faster near the outside of the semiconductor wafer 30 than at the center of the semiconductor wafer 30, which results in over-etching of the GTOs 10 near the outside of the semiconductor wafer 30 into the N-type base layers 18 of those GTOs 10, as illustrated in FIG. 3. As a result of the over-etching, the GTOs 10 in an outside area 32 (FIG. 2) of the semiconductor wafer 30 fail to operate as intended, which reduces yield. For example, due to over-etching, only 60%-70% of the GTOs 10 fabricated on the semiconductor wafer 30 may be usable (i.e., the yield may be only 60%-70%). As such, there is a need for an electronic device structure that increases yield and a method of fabricating the same.